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Job Description
Intel's Post Silicon Debug technology pathfinding team is responsible for next generation ion beam technology, circuit edit, and transistor probe technology developments. The Si Debug Pathfinding program manager will help lead a broad range of research to develop and identify new technologies and methodologies to support physical debug analysis capabilities on next generation 3D package / 3DIC data center, client, and GPU products. Responsibilities include:
Work with Intel product, process, and package pathfinding teams to identify capability needs and gaps.
Work with internal and external research ecosystem (Universities, National Labs, Equipment Suppliers) to identify new technologies to meet physical debug and fault isolation challenges.
Manage research programs and team members on research and development activities and design of experiments.
Work with government agencies on silicon debug strategic research initiatives
Execution of experiments for new generations of physical debug technologies / platforms including NG ion beam technologies, device prep technologies, and emission / irradiation based transistor probe technologies.
Additional responsibilities include:
Collaborating with the operation support team to develop and improve new debug processes for the current and next generation process nodes.
Working with circuit designers, component debug, and platform validation engineering on direct write device modification and node access strategies.
Working with process development engineers on developing best practices for defect analysis.
Good verbal and written communication skills, ability to create training, program updates, and quarterly report documentation
Ability to work both independently and collaboratively with teams across multiple organization and geographies.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Desired Experience in the following areas:
Silicon
Device physics and integrated circuit knowledge.
Circuit design and layout.
Semiconductor fabrication process
Silicon and package physical failure analysis.
Circuit Edit applications or related fields.
Contactless probe technology: e.g., IREM, LVP, LADA, LIT Thermal Imaging; OBIC, EBIC, etc.
Scanning Electron Microscopy, Transmission Electron Microscopy, Focused Ion Beam system operations.
UHV Vacuum technology.
Experience with government programs, e.g., DARPA, IARPA, DoD, DoC.
Inside this Business Group
Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Annual Salary Range for jobs which could be performed in US, California: $162,600.00-$284,620.00
*Salary range dependent on a number of factors including location and experience
Working Model
This role will require an on-site presence.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.